A conventional NAND-type flash memory requires a data transfer time (random access time) of about 7 μs to transfer data from a memory cell to a page buffer circuit. This time period depends on the layout of a memory cell array and the method of fetching data.
FIG. 1 is a block diagram showing the entire configuration of a general NAND-type flash memory. As showed in FIG. 1, the conventional general NAND-type flash memory 1 is provided with the following: a logic controller 3, a control circuit 5, an I/O control circuit 7, a command register 9, an address register 11, a status register 13, a state representation circuit 15, a terminal 16, a high voltage generation circuit 17, a row address buffer 19, a row address decoder 21, a memory cell array 23, a column address buffer 25, a column decoder 26, a data register 27, a bus OBUS, a sense amp 28, and an N-channel MOS transistor NT1.
A page buffer circuit PB is configured by the data register 27 and the sense amp 28. Additionally, the data register 27 includes the data latch circuit DL configuring the page buffer circuit PB, and the sense amp 28 includes a sense amp circuit SA configuring the page buffer circuit PB.
In the above NAND-type flash memory, the logic controller 3 is provided with a command enable signal /CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal /WE, and a read enable signal /RE.
On the other hand, the I/O control circuit 7 is connected to input terminals 6 to which signals I/O0-I/O7 are provided, further connected to the status register 13, and provided with the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal /WE, and an internal power supply voltage Vccq. The command register 9 and the address register 11 are connected to the I/O control circuit 7. The status register 13, the state representation circuit 15, and the high voltage generation circuit 17 are connected to the control circuit 5. The gate of the N-channel MOS transistor NT1 is connected to the state representation circuit 15 with its source being grounded and its drain being connected to the terminal 16 that outputs a busy signal /BY.
Additionally, the row address buffer 19 is connected to the address register 11, and the row address decoder 21 and the memory cell array 23 are connected to the high voltage generation circuit 17. Furthermore, the row address decoder 21 is connected to the control circuit 5, and the memory cell array 23 is connected to the row address decoder 21.
Additionally, the column address buffer 25 is connected to the address register 11, and the column decoder 26 is connected to the column address buffer 25. The data register 27 is connected to the I/O control circuit 7 via the bus OBUS and further to the column decoder 26. Furthermore, the sense amp 28 is connected between the data register 27 and the memory cell array 23, and further connected to the control circuit 5.
FIG. 2 is a schematic drawing showing the layout of the memory cell array 23 showed in FIG. 1, and FIG. 3 is a circuit diagram showing the equivalent circuit of the memory cell array 23 showed in FIG. 2. As showed in FIG. 2, the following are formed in the memory cell array 23: a plurality of bit lines BL connected to the page buffer circuit PB, a plurality of word lines WL0a-WL15a, WL0b-WL15b, and WL0c-WL15c, a plurality of select gate lines SG1a, SG2a, SG1b, SG2b, SG1c, the word lines and the select gate lines being perpendicular to the bit lines BL, a plurality of select gate transistors SGTr, and a plurality of memory cells MC, the select gate transistors SGTr and the memory cells MC being described later. The memory cells MC and the select gate transistors SGTr that are connected serially are connected to the bit lines BL via the bit line contact units BC.
On the other hand, FIG. 3(a) shows the entire configuration of the memory cell array 23, and FIG. 3(b) is a circuit diagram showing the configuration of a portion 29 showed in FIG. 3(a). In addition, in FIG. 3(a), the memory cell array 23 is simplified.
As showed in FIG. 3(a), the memory cell array is configured by a series of (N+1) blocks from the 0th block to the Nth block provided in the direction of the bit line BL. The memory cell array includes the bit lines BL connected to the page buffer circuit PB. And, as showed in FIG. 3(b), each block configuring the NAND-type flash memory includes a string ST connected to the bit lines BL. The string includes a plurality of serially connected memory cells MC and the select gate transistors SGTr serially connected on both sides.
A corresponding word line WL0a-WL15a, WL0b-WL15b, or WL0c-WL15c is connected to each gate of the above memory cell MC configured by a flash memory. A corresponding select gate line SG1a, SG2a, SG1b, SG2b, SG1c, or SG2c is connected to each gate of the select gate transistor SGTr.
Additionally, in the above configuration, the size of the page buffer circuit PB is correspondingly determined based on the page size, 528 bytes (4,224 bits), for example, being the unit of writing and reading of data of the NAND-type flash memory. When data are transferred, the page buffer amplifies and latches a whole page of data.
FIG. 4 is a circuit diagram showing the configuration of the page buffer circuit PB showed in FIG. 1. As showed in FIG. 4, the page buffer circuit PB is provided with the sense amp circuit SA, a data latch circuit DL, a tri-state buffer TSB, and N-channel MOS transistors NT2 and NT8.
The sense amp circuit SA includes N-channel MOS transistors NT9, NT10, and a P-channel MOS transistor PT3. The data latch circuit DL includes a latch circuit 30 and N-channel MOS transistors NT6 and NT7. And the tri-state buffer TSB includes N-channel MOS transistors NT3-NT5 and P-channel MOS transistors PT1 and PT2.
Here, the source and drain of the N-channel MOS transistor NT2 are connected in series to the bus OBUS, and a signal YD1 is provided to its gate from the column decoder 26. Additionally, the signal LD is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT5 and the gate of the P-channel MOS transistor PT2 and the signal RD is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT3. Likewise, a signal SET is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT7, and a signal PGMON is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT8.
Additionally, a signal BLCNTRL is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT9. A signal DIS is provided from the control circuit 5 to the gate of the N-channel MOS transistor NT10, and a signal PBIAS is provided from the control circuit 5 to the gate of the P-channel MOS transistor PT3. In addition, the source and drain of the N-channel MOS transistor NT9 are connected in series to the bit line BL.
In the page buffer circuit PB configured as described above, a high level signal BLCNTRL provided to the gate of the N-channel MOS transistor NT9 connects the bit line BL to the sense amp circuit SA. In addition, when data are transferred, a low level signal PBIAS provided to the gate of the P-channel MOS transistor PT3 causes the P-channel MOS transistor PT3 to provide sense current Iref to the bit line BL.
Additionally, the N-channel MOS transistor NT10, when a high level signal DIS is provided to its gate, discharges the bit line BL. In the initial stage of data transfer, when the N-channel MOS transistor NT8 is turned on in response to a signal PGMON, the N-channel MOS transistor NT10 resets the node A included in the latch circuit 30 to a low level.
On the other hand, the N-channel MOS transistors NT6 and NT7 are serially connected to a node B included in the latch circuit 30. The gate of the N-channel MOS transistor NT6 is connected to a node SNS. Accordingly, the N-channel MOS transistor NT6 turns on and off in response to data amplified by the sense amp SA. The data are latched by the latch circuit 30 in response to a signal SET provided to the gate of the N-channel MOS transistor NT7.
The above signals RD and LD turn to a high level when data are read from and loaded to the memory cell MC, respectively. For example, when the signal RD is turned to a high level, the tri-state buffer TSB is enabled. During this period, the tri-state buffer TSB inversely amplifies the signal level at the node A, and provides data generated by inversely amplifying to the bus OBUS via the N-channel MOS transistor NT2.
On the other hand, the signal LD, when it turns to a high level, disables the tri-state buffer TSB. Data are provided to the node A from the bus OBUS via the N-channel MOS transistor NT2 and NT5.
The data transfer operation of the NAND-type flash memory configured as above will be described by reference to timing charts showed in FIGS. 5 and 6 as follows. FIG. 5 shows timing in which data “0” of the memory cell array showed in FIGS. 2 and 3 are transferred.
As showed in FIG. 5(a), a command latch enable signal CLE is turned to a high level (H) at time T1 to start data transfer, and as showed in FIG. 5(c), a write enable signal /WE is turned to a low level (L). In response to these signals, as showed in FIG. 5(d), the flash memory acquires a command through the I/O terminal 6. This command is latched in the command register 9 when the write enable signal /WE turns to the high level (also referred to as “rise”). As showed in FIG. 5(g), in response to the above command indicating an instruction of the reading of data, the control circuit 5 turns the signal RD to a high level.
As showed in FIG. 5(b), an address latch enable signal ALE is turned to a high level at time T2, and as showed in FIG. 5(c), an address Add is input by toggling the write enable signal /WE. This address Add is latched by the address register 11 in response to a rise in the write enable signal /WE as well as the above command.
After the inputting of the address, the device automatically starts the data transfer operation. Specifically, as showed in FIGS. 5(e) and (f), the control circuit 5 turns a signal DIS and the signal PGMON to high levels at time T3. In response to this, as showed in FIGS. 5(n) and (o), the nodes A and B of the data latch circuit DL included in the page buffer circuit PB showed in FIG. 4 are reset to a low level and a high level, respectively.
In this case, as showed in FIGS. 5(j) and (k), select gate lines SG1a and SG2a of the selected block in the memory cell array are each activated to a high level of 4 V, for example, at time T4. Additionally, a selected word line is turned to a low level of 0 V, for example, and an unselected word line is turned to a high level of 4 V, for example.
Now, as showed in FIG. 5(i), a signal BLCNTRL is turned to a high level of 1.5 V, for example, and as showed in FIG. 5(h), a signal PBIAS is lowered so that a sense current Iref showed in FIG. 4 becomes a desired level of 1 μA, for example.
Therefore, the sense amp circuit SA included in the page buffer circuit PB is connected to the bit line BL, and the above sense current Iref flows in the bit line BL. And voltage caused by the difference between the sense current Iref and the current that flows through the selected memory cell MC appears as the voltage of the node SNS showed in FIG. 5(m).
When the memory cell MC does not stores data “0” as described above, no current flows in the memory cell MC. Accordingly, as showed in FIG. 5(m), the voltage at the node SNS starts rising at time T5 due to the above sense current Iref. And, as showed in FIG. 5(l), the control circuit 5 has a signal SET transit to a high level at time T6 after a long enough time passes for the voltage of the node SNS to be stabilized at a high level.
Because, as showed in FIG. 5(m), the voltage of the node SNS is at a high level, the N-channel MOS transistor NT7 showed in FIG. 4 turns on, and the node B of the data latch circuit DL is drawn to the low level. As showed in FIGS. 5(n) and (o), the node A turns to a high level and the node B turns to a low level at time T7. In response to this, data output at the node A are inverted by the tri-state buffer TSB, and data “0” are provided to the I/O control circuit 7 via the bus OBUS. The I/O control circuit 7 outputs data “0” to the exterior through the I/O pins 6.
The reading operation of data “0” in the case of a conventional NAND-type flash memory has been described above. The transfer operation of data “0” of the memory cell array showed in FIGS. 2 and 3 will be described by reference to FIG. 6. Since the inputting of the command and the address is the same as the reading operation of data “0” described above, its description will not be given.
As showed in FIGS. 6(e) and (f), the control circuit 5 turns the signal DIS and the signal PGMON to high levels at time T3 after the inputting of the address. Consequently, in the data latch circuit DL showed in FIG. 4, the node A and the node B are reset to a low level and a high level, respectively. The select gate lines SG1a and SG2a included in a selected block in the memory cell array are each turned to a high level at time T4, a selected word line is turned to a low level, and an unselected word line is turned to a high level.
As showed in FIG. 6(i), the signal BLCNTRL is turned to a high level at time T5, and the signal PBIAS is lowered so that the sense current Iref showed in FIG. 4 becomes at a desired level.
The sense amp circuit SA included in the page buffer circuit PB is connected to the bit line BL, and the above sense current Iref flows through the bit line BL. The difference between the sense current Iref and the current flowing through the selected memory cell MC results in voltage at the node SNS showed in FIG. 6(m).
Now, when the memory cell MC stores data “1” as described above, the memory cell MC causes the current flow so that, as showed in FIG. 6(m), the node SNS is discharged to a low level. And, the control circuit 5 has the signal SET transit to a high level at time T6 after a long enough time passes for the voltage of the node SNS to stabilize at a low level.
At this point, since the voltage of the node SNS is at a low level as showed in FIG. 6(m), the node B of the data latch circuit DL sustains a high level state, and, as showed in FIGS. 6(n) and (o), the nodes A and B become at a low level and at a high level, respectively. Consequently, data output at the node A are inverted by the tri-state buffer TSB, and data “1” are provided to the I/O control circuit 7 through the bus OBUS. In addition, the I/O control circuit 7 outputs the data “1” to the exterior through the I/O terminal 6.
In accordance with the above description, time required for completing the reading operation (data transfer) of data “0” is, as showed in FIG. 5, the sum of the time period Ta from time T3 to time T4 and time period Tb from time T4 to time T7. The time Ta is, as described above, time required to reset the data latch circuit DL and to set the select gate lines SG1a, SG2a, in a selected block, and the unselected word line at a high level. The time Tb is time required to charge the bit line BL with the sense current Iref so that the voltage of the node SNS is stabilized at the high level. The above times Ta and Tb may overlap depending on the case.
In addition, the above time Tb depends on the following: the capacitance and resistance of the bit line BL, the capacitance of the diffusion layer of the select gate transistor SGTr connected to the bit line BL, and the above sense current Iref.